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- Alliance - VLSI CAD system
- A complete set of free CAD tools and portable libraries for VLSI design.
- Covered - Verilog Code Coverage Analyzer
- A Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test.
- FreeHDL Project
- A free and open VHDL simulator for Linux.
- Gerbv - A Free Gerber Viewer
- A utility for displaying CAD files that are used in the manufacture of electronic printed circuit boards. It is one of the utilities affiliated with the gEDA project.
- Icarus Verilog
- A Verilog simulation and synthesis tool; it operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
- Open Collector
- Database of open hardware designs and design programs (especially the EDA end of hardware design).
- The gEDA Project
- A GPL'd suite of tools used for electrical circuit design, schematic capture, simulation, prototyping, and production.
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