[Discuss] FW: Kernel interpretation of pressing the reset button?

[Deryk Barker (Honorary Colleague)]

From: Discuss [discuss-bounces at vlug.org] on behalf of Cy Schubert [Cy.Schubert at cschubert.com]
Sent: Monday, June 11, 2018 5:46 PM
To: discuss at vlug.org
Subject: Re: [Discuss] Kernel interpretation of pressing the reset  button?

>In message <4E6AE5F528744E479C4F2AC326FFF840024809C631 at EX10MBX01.intra.c
amosun.
bc.ca>, "Deryk Barker (Honorary Colleague)" writes:
>> Well, I *did* say unless things have changed.
>>
>> Certainly on the old PCI bus there was a line called RESET and *all* the butt
>> on did was assert this line. It was up to the CPU to notice it.

> Can you explain to us how the CPU notices it?

Presumably the same way it sees any other external signal: by sampling the pin.

>>
>> Looking around there does not seem to be complete agreement these days and wi
>> kipedia (I know, I know...) says:
>>
>> "On personal computers,[NB 1] the reset button clears the memory and reboots
>> the machine forcibly."
>>
>> before, a few paragraphs later, saying"
>>
>> "Reset buttons or keypresses on any computer cannot erase the contents of sys
>> tem RAM, which can only be done by powering the computer off and waiting appr
>> oximately 10 seconds for residual current in the RAM chips to dissipate."
>>
>> So, the button either clears the memory or it doesn't...

> When the reset pin is asserted and the CPU is reset, it starts
> executing at FFF0:0000h. Motherboard manufactures are cagey about
> whether the reset jumper clears memory or not. Does it matter if memory
> is cleared or not? Remember all the registers are reset to zero. If you
> say it does matter, please explain why it does. Remember again, all
> registers are cleared.

I did not claim that it mattered or, indeed, that it was or was not cleared, merely pointed out that the information available online is not consistent.

Incidentally, according to https://en.wikipedia.org/wiki/Reset_vector the address held in the reset vector is different for different architectures (as one would expect) and for the x86 series is FFFF0000h:FFF0h.

Also, the reset line should be sampled by the various device controllers to reset themselves.

deryk
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